Oliveira, José Alberto Nicolau dePrado, Rafael Nunes de Almeida2014-12-172011-06-222014-12-172011-02-22PRADO, Rafael Nunes de Almeida. Desenvolvimento de uma arquitetura em hardware prototipada em FPGA para aplicações genéricas utilizando redes neurais artificiais embarcadas. 2011. 94 f. Dissertação (Mestrado em Automação e Sistemas; Engenharia de Computação; Telecomunicações) - Universidade Federal do Rio Grande do Norte, Natal, 2011.https://repositorio.ufrn.br/jspui/handle/123456789/15342This work proposes hardware architecture, VHDL described, developed to embedded Artificial Neural Network (ANN), Multilayer Perceptron (MLP). The present work idealizes that, in this architecture, ANN applications could easily embed several different topologies of MLP network industrial field. The MLP topology in which the architecture can be configured is defined by a simple and specifically data input (instructions) that determines the layers and Perceptron quantity of the network. In order to set several MLP topologies, many components (datapath) and a controller were developed to execute these instructions. Thus, an user defines a group of previously known instructions which determine ANN characteristics. The system will guarantee the MLP execution through the neural processors (Perceptrons), the components of datapath and the controller that were developed. In other way, the biases and the weights must be static, the ANN that will be embedded must had been trained previously, in off-line way. The knowledge of system internal characteristics and the VHDL language by the user are not needed. The reconfigurable FPGA device was used to implement, simulate and test all the system, allowing application in several real daily problemsapplication/pdfAcesso AbertoSistemas EmbarcadosRedes Neurais ArtificiaisRTL DesignFPGAVHDLEmbedded systemsArtificial neural networkRTL designFPGAVHDLmasterThesisCNPQ::ENGENHARIAS::ENGENHARIA ELETRICA