Programa de Pós-Graduação em Engenharia Elétrica e de Computação
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Doctoral Thesis Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications(Universidade Federal do Rio Grande do Norte, 2024-12-11) Santos Júnior, Carlos Eduardo de Barros; Fernandes, Marcelo Augusto Costa; Silva, Sérgio Natan; https://orcid.org/0000-0001-7536-2506; http://lattes.cnpq.br/3475337353676349; http://lattes.cnpq.br/1334493042199015; Dias, Leonardo Alves; Silva, Lucileide Medeiros Dantas da; Coutinho, Maria Gracielly FernandesAs IoT device usage continues to expand, ensuring secure, low-latency data exchange has become essential, driving research into blockchain-based solutions to meet these requirements. Addressing this demand, this thesis presents a reconfigurable hardware architecture for the SHA-256 hash algorithm, focusing on blockchain and IoT applications, utilizing Field Programmable Gate Arrays (FPGAs) as the target hardware to maximize performance and efficiency in data security processes. The proposed FPGA implementation provides adaptability across various environments, from network servers to energyconstrained IoT devices. Key innovations in this proposal include a multicore parallelism system that optimizes the use of available FPGA resources and a structured analysis of resource consumption, considering both clock frequency and throughput. Additionally, the thesis provides a power consumption analysis, comparing power efficiency across different hardware architectures. The proposed design achieved the implementation of 16 parallel cores on a Xilinx Virtex 6 xc6vlx240t-1ff1156 FPGA, reaching a maximum throughput of 1.4Gbps and dynamic power consumption of 0.452W. This performance represents up to 16x speedup over previous FPGA models and a reduction of up to 234.52x in dynamic power consumption compared to implementations from prior research. Additional comparisons were conducted with other hardware architectures, such as 8- and 16-bit microcontrollers, general-purpose processors, and GPUs. The results underscore the versatility and scalability of FPGA-based SHA-256 implementations for applications requiring high throughput and power efficiency, establishing this work as a significant contribution to information security and computational performance in IoT environments within a blockchain context.Master Thesis Proposta de implementação dos algoritmos de hash MD5 e SHA-1 em hardware reconfigurável(2018-06-20) Santos Júnior, Carlos Eduardo de Barros; Fernandes, Marcelo Augusto Costa; ; ; Cansian, Adriano Mauro; ; Silva, Carlos Eduardo da; ; Silva, Ivanovitch Medeiros Dantas da; ; Roda, Valentin Obac;This work proposes two Application Specific System Processor (ASSP), one to the MD5 algorithm and other to the SHA-1 algorithm implemented on Field Programmable Gate Array (FPGA) Xilinx Virtex 6 xc6vlx240t-1ff1156. The throughput and the occupied area were analyzed for several implementations on parallel instances of those algorithms. The results showed that the hardware proposed for MD5 achieved a better throughput than those found in published articles and it was possible to implement 320 instances of the algorithm in a single FPGA. For the SHA-1 algorithm the throughput and the area occupied by the internal circuits on the chip were also surprising when compared with other papers. Several applications such as password recovery, password validation, and high volume data integrity checking can be performed efficiently and quickly with an ASSP for MD5 and SHA-1. This work also presents a comparative analysis of the energy consumption associated with execution of the MD5 and SHA-1 algorithms for three different hardware platforms, a microprocessor (µP) of 8 bits and 32 bits and the specific application hardware designed for each algorithm. Results of consumption estimation from the processing time (measured in the laboratory) show that the use of dedicated hardware presents significant gains in energy savings.