Programa de Pós-Graduação em Engenharia Elétrica e de Computação
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Doctoral Thesis Modelo comportamental do capacitor ferroelétrico como unidade básica de neurônios artificiais e sua implementação em FPGA(Universidade Federal do Rio Grande do Norte, 2015-01-30) Silva, Alan Paulo Oliveira da; Guerreiro, Ana Maria Guimarães; ; http://lattes.cnpq.br/8556144121380013; ; http://lattes.cnpq.br/3077032897407238; Lopes, Danniel Cavalcante; ; http://lattes.cnpq.br/5342832426660173; Soares, Heliana Bezerra; ; http://lattes.cnpq.br/5057165446370629; Fernandes, Marcelo Augusto Costa; ; http://lattes.cnpq.br/3475337353676349; Sablon, Vicente Idalberto Becerra; ; http://lattes.cnpq.br/6350047853320576This work proposes the use of the behavioral model of the hysteresis loop of the ferroelectrics capacitor as a new alternative to the usually costly techniques in the computation of nonlinear functions in artificial neurons implemented on reconfigurable hardware platform, in this case, a FPGA device. Initially the proposal has been validated by the implementation of the boolean logic through the digital models of two artificial neurons: the Perceptron and a variation of the model Integrate and Fire Spiking Neuron, both using the model also digital of the hysteresis loop of the ferroelectric capacitor as it’s basic nonlinear unit for the calculations of the neurons outputs. Finally, it has been used the analog model of the ferroelectric capacitor with the goal of verifying it’s effectiveness and possibly the reduction of the number of necessary logic elements in the case of implementing the artificial neurons on integrated circuit. The implementations has been carried out by Simulink models and the synthesizing has been done through the DSP Builder software from Altera Corporation.Master Thesis Uma implementação da análise de componentes independentes em plataforma de hardware reconfigurável(Universidade Federal do Rio Grande do Norte, 2010-02-19) Silva, Alan Paulo Oliveira da; Guerreiro, Ana Maria Guimarães; ; http://lattes.cnpq.br/8556144121380013; ; http://lattes.cnpq.br/3077032897407238; Dória Neto, Adrião Duarte; ; http://lattes.cnpq.br/1987295209521433; Brandão, Gláucio Bezerra; ; http://lattes.cnpq.br/0050402182466103; Lopes, Danniel Cavalvante;Blind Source Separation (BSS) refers to the problem of estimate original signals from observed linear mixtures with no knowledge about the sources or the mixing process. Independent Component Analysis (ICA) is a technique mainly applied to BSS problem and from the algorithms that implement this technique, FastICA is a high performance iterative algorithm of low computacional cost that uses nongaussianity measures based on high order statistics to estimate the original sources. The great number of applications where ICA has been found useful reects the need of the implementation of this technique in hardware and the natural paralelism of FastICA favors the implementation of this algorithm on digital hardware. This work proposes the implementation of FastICA on a reconfigurable hardware platform for the viability of it's use in blind source separation problems, more specifically in a hardware prototype embedded in a Field Programmable Gate Array (FPGA) board for the monitoring of beds in hospital environments. The implementations will be carried out by Simulink models and it's synthesizing will be done through the DSP Builder software from Altera Corporation.