Programa de Pós-Graduação em Engenharia Elétrica e de Computação
Permanent URI for this communityhttps://repositorio.ufrn.br/handle/123456789/11949
Browse
2 results
Search Results
Doctoral Thesis Implementação de uma matriz de neurônios dinamicamente reconfigurável para descrição de topologias de redes neurais artificiais multilayer perceptrons(Universidade Federal do Rio Grande do Norte, 2015-09-04) Silva, Carlos Alberto de Albuquerque; Dória Neto, Adrião Duarte; ; http://lattes.cnpq.br/1987295209521433; ; http://lattes.cnpq.br/7963808444142138; Barbalho, David Simonetti; ; http://lattes.cnpq.br/7208859488227503; Melo, Jorge Dantas de; ; http://lattes.cnpq.br/7325007451912598; Oliveira, José Alberto Nicolau de; ; http://lattes.cnpq.br/2871134011057075; Lopes, Danniel Cavalcante; ; http://lattes.cnpq.br/5342832426660173; Ramos, Karla Darlene Nepomuceno; ; http://lattes.cnpq.br/2751239628595747The Artificial Neural Networks (ANN), which is one of the branches of Artificial Intelligence (AI), are being employed as a solution to many complex problems existing in several areas. To solve these problems, it is essential that its implementation is done in hardware. Among the strategies to be adopted and met during the design phase and implementation of RNAs in hardware, connections between neurons are the ones that need more attention. Recently, are RNAs implemented both in application specific integrated circuits's (Application Specific Integrated Circuits - ASIC) and in integrated circuits configured by the user, like the Field Programmable Gate Array (FPGA), which have the ability to be partially rewritten, at runtime, forming thus a system Partially Reconfigurable (SPR), the use of which provides several advantages, such as flexibility in implementation and cost reduction. It has been noted a considerable increase in the use of FPGAs for implementing ANNs. Given the above, it is proposed to implement an array of reconfigurable neurons for topologies Description of artificial neural network multilayer perceptrons (MLPs) in FPGA, in order to encourage feedback and reuse of neural processors (perceptrons) used in the same area of the circuit. It is further proposed, a communication network capable of performing the reuse of artificial neurons. The architecture of the proposed system will configure various topologies MLPs networks through partial reconfiguration of the FPGA. To allow this flexibility RNAs settings, a set of digital components (datapath), and a controller were developed to execute instructions that define each topology for MLP neural network.Master Thesis Contribuição para o estudo do embarque de uma rede neural artificial em field programmable gate array (FPGA)(Universidade Federal do Rio Grande do Norte, 2010-06-30) Silva, Carlos Alberto de Albuquerque; Dória Neto, Adrião Duarte; Oliveira, José Alberto Nicolau de; ; http://lattes.cnpq.br/2871134011057075; ; http://lattes.cnpq.br/1987295209521433; ; http://lattes.cnpq.br/7963808444142138; Melo, Jorge Dantas de; ; http://lattes.cnpq.br/7325007451912598; Lopes, Danniel Cavalvante;This study shows the implementation and the embedding of an Artificial Neural Network (ANN) in hardware, or in a programmable device, as a field programmable gate array (FPGA). This work allowed the exploration of different implementations, described in VHDL, of multilayer perceptrons ANN. Due to the parallelism inherent to ANNs, there are disadvantages in software implementations due to the sequential nature of the Von Neumann architectures. As an alternative to this problem, there is a hardware implementation that allows to exploit all the parallelism implicit in this model. Currently, there is an increase in use of FPGAs as a platform to implement neural networks in hardware, exploiting the high processing power, low cost, ease of programming and ability to reconfigure the circuit, allowing the network to adapt to different applications. Given this context, the aim is to develop arrays of neural networks in hardware, a flexible architecture, in which it is possible to add or remove neurons, and mainly, modify the network topology, in order to enable a modular network of fixed-point arithmetic in a FPGA. Five synthesis of VHDL descriptions were produced: two for the neuron with one or two entrances, and three different architectures of ANN. The descriptions of the used architectures became very modular, easily allowing the increase or decrease of the number of neurons. As a result, some complete neural networks were implemented in FPGA, in fixed-point arithmetic, with a high-capacity parallel processing