Programa de Pós-Graduação em Engenharia Elétrica e de Computação
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Doctoral Thesis Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications(Universidade Federal do Rio Grande do Norte, 2024-12-11) Santos Júnior, Carlos Eduardo de Barros; Fernandes, Marcelo Augusto Costa; Silva, Sérgio Natan; https://orcid.org/0000-0001-7536-2506; http://lattes.cnpq.br/3475337353676349; http://lattes.cnpq.br/1334493042199015; Dias, Leonardo Alves; Silva, Lucileide Medeiros Dantas da; Coutinho, Maria Gracielly FernandesAs IoT device usage continues to expand, ensuring secure, low-latency data exchange has become essential, driving research into blockchain-based solutions to meet these requirements. Addressing this demand, this thesis presents a reconfigurable hardware architecture for the SHA-256 hash algorithm, focusing on blockchain and IoT applications, utilizing Field Programmable Gate Arrays (FPGAs) as the target hardware to maximize performance and efficiency in data security processes. The proposed FPGA implementation provides adaptability across various environments, from network servers to energyconstrained IoT devices. Key innovations in this proposal include a multicore parallelism system that optimizes the use of available FPGA resources and a structured analysis of resource consumption, considering both clock frequency and throughput. Additionally, the thesis provides a power consumption analysis, comparing power efficiency across different hardware architectures. The proposed design achieved the implementation of 16 parallel cores on a Xilinx Virtex 6 xc6vlx240t-1ff1156 FPGA, reaching a maximum throughput of 1.4Gbps and dynamic power consumption of 0.452W. This performance represents up to 16x speedup over previous FPGA models and a reduction of up to 234.52x in dynamic power consumption compared to implementations from prior research. Additional comparisons were conducted with other hardware architectures, such as 8- and 16-bit microcontrollers, general-purpose processors, and GPUs. The results underscore the versatility and scalability of FPGA-based SHA-256 implementations for applications requiring high throughput and power efficiency, establishing this work as a significant contribution to information security and computational performance in IoT environments within a blockchain context.Master Thesis Hardware implementation of the Otsu's method applied to realtime worm segmentation(Universidade Federal do Rio Grande do Norte, 2021-11-17) Barros, Wysterlânya Kyury Pereira; Fernandes, Marcelo Augusto Costa; http://lattes.cnpq.br/3475337353676349; http://lattes.cnpq.br/2532477079704883; Gomes, Rafael Beserra; http://lattes.cnpq.br/5849107545126304; Brito Júnior, Agostinho de Medeiros; Carvalho, Marco Antonio Garcia de; http://lattes.cnpq.br/6366443994619479Behavioral genomic studies employing the worm Caenorhabditis elegans have aided the discovery of new gene-behavioral associations and the screening of new drugs. Highresolution cameras record experiments with this worm, generating videos that computational solutions will later process for automated behavioral analysis. Because of the large volume of data to be processed, these analyses usually have to be performed offline. However, it is desired to develop a high-throughput implementation capable of operating in real-time, seeking to reduce the memory occupation by storing videos and allow the realization of new kinds of experiments. One way to speed up the algorithms employed is through the use of reconfigurable computing. Therefore, this work proposes the hardware development of the Otsu method for worm segmentation in real-time. The proposed implementation was developed in Field Programmable Gate Array (FPGA) using a fully parallel strategy with fixed-point representation. Architecture details are presented, as well as synthesis results related to the hardware area occupation, throughput, and dynamic power consumption. Results about validation of the implementation using images of the worms are also provided. The data show that the proposed architecture can achieve high speedups compared to similar work presented in the literature, besides allowing the segmentation of worms in real-time.Doctoral Thesis Reconfigurable computing applied to latency reduction in control and prediction systems focused on tactile internet(Universidade Federal do Rio Grande do Norte, 2021-01-28) Silva, Sérgio Natan; Fernandes, Marcelo Augusto Costa; ; ; http://lattes.cnpq.br/3735623063336406; Silva, Ivanovitch Medeiros Dantas da; ; Silva Júnior, José Cláudio Vieira e; ; Dias, Leonardo Alves; ; Oliveira, Luiz Affonso Henderson Guedes de;The Tactile Internet is the current technological advance for the Internet. This new paradigm enables the sending of touch information, as well as the other stimuli already sent. Thus, it is necessary to guarantee a very low latency between the devices that make up the tactile interaction. The time of propagation of information through the communication channel, processing power of local devices, the complexity of the techniques, among others, can be the cause of the system latency. This work proposes the use of dedicated hardware-based reconfigurable computing (RC) to reduce latency in control and prediction systems applied to the Tactile Internet. Two approaches are proposed to address the latency issue. In the first approach, proposes the implementation of linear and non-linear prediction techniques in RC. In this approach, prediction techniques are used to minimize the impacts caused by delays and loss of information. The second approach an intelligent control system based on Fuzzy logic in RC is proposed. The system is a Takagi - Sugeno Fuzzy-PI type controller that aims to reduce the latency associated with processing the tool’s control data. The implementation uses a completely parallel strategy associated with a hybrid bit format scheme (fixed-point and floating-point). Still in this approach, two hardware projects are proposed: the first uses a single clock cycle processing architecture and the other uses a pipeline scheme. The proposals are implemented in a Field Programmable Gate Array on the Virtex 6 xc6vlx240t-1ff1156 platform. Data related to occupation and throughput associated with the target platform are presented, as well as a comparison between results through simulation and implementations in dedicated hardware. The results are superior to those presented in other studies in the literature.Master Thesis Fully parallel implementation of an SVM with SGD-based training on FPGA(Universidade Federal do Rio Grande do Norte, 2021-01-29) Lopes, Felipe Fernandes; Fernandes, Marcelo Augusto Costa; ; http://lattes.cnpq.br/3475337353676349; ; http://lattes.cnpq.br/8291687873735152; Silva, Ivanovitch Medeiros Dantas da; ; http://lattes.cnpq.br/3608440944832201; Santana Júnior, Orivaldo Vieira de; ; http://lattes.cnpq.br/5050555219716698; Sablon, Vicente Idalberto Becerra; ; http://lattes.cnpq.br/6350047853320576Artificial intelligence, machine learning, and deep learning have proven to be powerful techniques for solving natural language processing problems, computer vision, and others. However, its computational and statistical performance depends on other factors of the algorithms used for training, the computing platform used, and even the numerical precision used to represent the data. One of the main machine learning algorithms is the Support Vector Machine (SVM), most commonly trained through minimal sequential optimization, contributing to low computational performance. As an alternative, algorithms based on Stochastic Gradient Descent (SGD) have better scalability and can be used as good options for training machine learning algorithms. However, even with algorithms based on the stochastic gradient, the training and inference times can become long depending on the computing platform employed. Thus, accelerators based on Field Programmable Gate Arrays (FPGAs) can be used to improve performance in terms of processing speed. This work proposes a fully parallel FPGA implementation of an SVM with SGD-based training. Results associated with hardware occupation, processing speed (or throughput), and accuracy for training and inference in various quantization formats are presented.Doctoral Thesis Hardware strategies applied to the latency reduction on tactile internet(Universidade Federal do Rio Grande do Norte, 2020-02-28) Silva Júnior, José Cláudio Vieira e; Fernandes, Marcelo Augusto Costa; ; ; Oliveira, Lucas M.; ; Aranibar, Dennis Barrios; ; Silva, Ivanovitch Medeiros Dantas da; ; Oliveira, José Alberto Nicolau de;This work proposes to present hardware strategies applied to reduce latency in the tactile internet. The motivation is to study the challenges contained in the development of the hardware associated with the tactile devices, especially issues related to the round trip latency limit of the system components. As is known, for a tactile internet environment to work desirably, it is necessary to respect a minimum limit of round trip latency. Since some tactile applications allow some human senses to interact with the machines remotely, this means that, almost always, the minimum limit of round trip latency has a time delay in the range of milliseconds. Thus, it is clear that there is a demand for tactile devices that are quite fast. In this context, three hardware proposals are presented that have the main objective to reduce the total latency produced by this type of device. The first strategy proposed for the development of hardware is to use reconfigurable computing (on FPGA) to minimize the execution time of the algorithms associated with the device. The second hardware proposal also makes use of reconfigurable computing (on FPGA). However, the hardware is designed using another type of numerical representation. Finally, the third proposal presents a tactile glove model implemented using a variety of micro processed system. Results associated with the three proposals are presented and show the viability of the strategies, presenting better performance concerning the works that were compared.Master Thesis Development of an FPGA-based real-time power system simulator for traveling wave-based protective relay validation(2019-09-06) Leal, Marcos Sérgio Rodrigues; Costa, Flávio Bezerra; ; ; Fernandes, Marcelo Augusto Costa; ; Ribeiro, Ricardo Lúcio de Araújo; ; Rocha, Thiago de Oliveira Alves; ; Neves, Washington Luiz Araújo;In this work a real-time digital simulator of power systems is implemented using a low-cost custom platform based on FPGA (field-programmable gate array) proper to perform real-time validation of traveling-wave-based transmission line protections. The operational view of the simulator is introduced by means of the modeling, implementation, and simulation steps of a transmission system, which is used to highlight the simulator capability to represent high-frequency transient phenomenon taking place transmission lines. Hence, at first, the mathematical models of the power system used in the case study are presented as well as the solver design, which is developed based on the electromagnetic transients program (EMTP). Then, the simulator characteristics, such as the hardware architecture, development software, communication strategies, graphical interface, input/output, and data export, are introduced, as well as the implementation stages of the test system. Moreover, it addresses the implementation of a relay prototype using a hardware based on DSP (digital signal processor), running an existing traveling-wavebased protection scheme, besides its closed-loop integration with the simulation. A GUI (graphical user interface) is developed to set the simulation parameters, including the conditions for applying an electrical fault, and to monitor the dynamic of the power system used as a case study. Off-line simulations obtained from Matlab/Simulink are used to validate the real-time results.Master Thesis Proposta de implementação em hardware de rede neural profunda baseada em Stacked Sparse Autoencoder(2019-01-17) Coutinho, Maria Gracielly Fernandes; Fernandes, Marcelo Augusto Costa; ; ; Doria Neto, Adrião Duarte; ; Sakuyama, Carlos Alberto Valderrama; ; Belfort, Diomadson Rodrigues;The deep learning techniques have been gaining prominence in world research in the past years. However, the deep learning algorithms have high computational cost, making it hard to apply in several commercial applications. On the other hand, new alternatives have been studying to accelerate complex algorithms, among these, those based on reconfigurable hardware has been showing very significant results. Therefore, the objective of this work is the hardware implementation of a neural network for the use of algorithms with deep learning. The hardware was developed on Field Programmable Gate Array (FPGA) and supports Deep Neural Network (DNN) trained with the Stacked Sparse Autoencoder (SSAE) technique. In order to allow DNNs with many inputs and layers on the FPGA, the systolic array technique was used in all developed hardware. The details of the architecture designed on the FPGA were evidenced, as well as the occupation data on hardware, the processing time and the power consumption to two different implementations. The results show that both implementations achieve high throughputs allowing the use of Deep Learning techniques in massive data problems.Master Thesis Simulador de Tempo Real para Sistemas Dinâmicos em FPGA(2016-07-22) Silva, Sergio Natan; Fernandes, Marcelo Augusto Costa; ; http://lattes.cnpq.br/3475337353676349; ; Pedrosa, Diogo Pinheiro Fernandes; ; Lima, Eduardo Rodrigues De; ; Silva, Ivanovitch Medeiros Dantas Da;The development of new algorithms embedded for automation and control of industrial equipment usually require the use of real-time testing . However, the equipment required is often expensive, which means that such tests are not viable. This work aims at the development of an embedded platform in Field Programmable Gate Array (FPGA) for real-time simulation of dynamic systems associated with industrial plants. The platform called Simulator Real-Time for Dynamic Systems in FPGA (STRSD-FPGA) can be applied in industrial and academic settings. In industry the STRSD-FPGA can be used in optimizing and tuning of embedded control algorithms. In the academic sphere, will be used in research on new embedded solutions for the field of automation and control, as well as a support tool to undergraduate teaching and graduate in the development of embedded control systems projects. The simulator may, further, enable the acceleration of the simulation for cases of very slow dynamic systems, enabling a reduction in the total simulation time.Master Thesis Proposta de implementação dos algoritmos de hash MD5 e SHA-1 em hardware reconfigurável(2018-06-20) Santos Júnior, Carlos Eduardo de Barros; Fernandes, Marcelo Augusto Costa; ; ; Cansian, Adriano Mauro; ; Silva, Carlos Eduardo da; ; Silva, Ivanovitch Medeiros Dantas da; ; Roda, Valentin Obac;This work proposes two Application Specific System Processor (ASSP), one to the MD5 algorithm and other to the SHA-1 algorithm implemented on Field Programmable Gate Array (FPGA) Xilinx Virtex 6 xc6vlx240t-1ff1156. The throughput and the occupied area were analyzed for several implementations on parallel instances of those algorithms. The results showed that the hardware proposed for MD5 achieved a better throughput than those found in published articles and it was possible to implement 320 instances of the algorithm in a single FPGA. For the SHA-1 algorithm the throughput and the area occupied by the internal circuits on the chip were also surprising when compared with other papers. Several applications such as password recovery, password validation, and high volume data integrity checking can be performed efficiently and quickly with an ASSP for MD5 and SHA-1. This work also presents a comparative analysis of the energy consumption associated with execution of the MD5 and SHA-1 algorithms for three different hardware platforms, a microprocessor (µP) of 8 bits and 32 bits and the specific application hardware designed for each algorithm. Results of consumption estimation from the processing time (measured in the laboratory) show that the use of dedicated hardware presents significant gains in energy savings.Doctoral Thesis LP-P2IP: uma versão de baixo consumo da arquitetura P2IP usando reconfiguração parcial em FPGA(2017-06-09) Avelino, Álvaro Medeiros; Roda, Valentin Obac; http://lattes.cnpq.br/4823406157799513; http://lattes.cnpq.br/3771815975074527; Oliveira, José Alberto Nicolau de; http://lattes.cnpq.br/2871134011057075; Melo, Júlio César Paulino de; http://lattes.cnpq.br/2930421117873633; Sakuyama, Carlos Alberto Valderrama; http://lattes.cnpq.br/4405442140445324; Marques, Eduardo; Pedrino, Emerson Carlos; http://lattes.cnpq.br/6481363465527189