Analytical speedup modeling for parallel applications with variable memoryaccess delay in symmetric architectures

Abstract

Several analytical models created since Amdahl’s pioneering work have explored aspects such as variation in the size of the problem, memory size, communication overhead, and synchronization overhead. However, delays in memory access are considered constant. Such delays can vary, for example, according to the number of cores, the relationship between the processor and memory frequencies, and the problem size. Given different problem sizes and many possible configurations of operational frequency and number of cores that current architectures can offer, speedup models suitable for describing such differences are quite desirable for either offline or online scheduling decisions. This thesis presents a novel analytical speedup model that considers variations in the average data-access delay to describe the limiting effect of the memory wall in parallel applications associated with homogeneous shared memory architectures. The experimental results indicate that the proposed model incorporates the behavior of the application adequately. The approach presented in this work shows that considering parameters that reflect the intrinsic characteristics of applications has advantages over statistical models such as those based on machine learning. The experiments also show that the conventional machine learning modeling may require measurements with one order of magnitude above to achieve the same accuracy level when compared with the proposed model.