Hardware strategies applied to the latency reduction on tactile internet

Abstract

This work proposes to present hardware strategies applied to reduce latency in the tactile internet. The motivation is to study the challenges contained in the development of the hardware associated with the tactile devices, especially issues related to the round trip latency limit of the system components. As is known, for a tactile internet environment to work desirably, it is necessary to respect a minimum limit of round trip latency. Since some tactile applications allow some human senses to interact with the machines remotely, this means that, almost always, the minimum limit of round trip latency has a time delay in the range of milliseconds. Thus, it is clear that there is a demand for tactile devices that are quite fast. In this context, three hardware proposals are presented that have the main objective to reduce the total latency produced by this type of device. The first strategy proposed for the development of hardware is to use reconfigurable computing (on FPGA) to minimize the execution time of the algorithms associated with the device. The second hardware proposal also makes use of reconfigurable computing (on FPGA). However, the hardware is designed using another type of numerical representation. Finally, the third proposal presents a tactile glove model implemented using a variety of micro processed system. Results associated with the three proposals are presented and show the viability of the strategies, presenting better performance concerning the works that were compared.