Reconfigurable hardware architecture for SHA-256 hashing in blockchain and IoT applications

Abstract

As IoT device usage continues to expand, ensuring secure, low-latency data exchange has become essential, driving research into blockchain-based solutions to meet these requirements. Addressing this demand, this thesis presents a reconfigurable hardware architecture for the SHA-256 hash algorithm, focusing on blockchain and IoT applications, utilizing Field Programmable Gate Arrays (FPGAs) as the target hardware to maximize performance and efficiency in data security processes. The proposed FPGA implementation provides adaptability across various environments, from network servers to energyconstrained IoT devices. Key innovations in this proposal include a multicore parallelism system that optimizes the use of available FPGA resources and a structured analysis of resource consumption, considering both clock frequency and throughput. Additionally, the thesis provides a power consumption analysis, comparing power efficiency across different hardware architectures. The proposed design achieved the implementation of 16 parallel cores on a Xilinx Virtex 6 xc6vlx240t-1ff1156 FPGA, reaching a maximum throughput of 1.4Gbps and dynamic power consumption of 0.452W. This performance represents up to 16x speedup over previous FPGA models and a reduction of up to 234.52x in dynamic power consumption compared to implementations from prior research. Additional comparisons were conducted with other hardware architectures, such as 8- and 16-bit microcontrollers, general-purpose processors, and GPUs. The results underscore the versatility and scalability of FPGA-based SHA-256 implementations for applications requiring high throughput and power efficiency, establishing this work as a significant contribution to information security and computational performance in IoT environments within a blockchain context.