Education RTL-To-GSDII Flow for an IEEE754 Single Precision Floating Point Multiplier

Abstract

This paper provides a detailed, step-by-step guide to the digital Application Specific Integrated Circuit (ASIC) design flow, illustrated through the case study of an IEEE 754 single- precision floating-point multiplier. The emphasis is not on implementing or optimizing the multiplier itself, but on explaining the characteristics, procedures, and outcomes at each stage of the design process. By thoroughly documenting these steps, the work aims to clarify how such a flow operates in practice and to serve as a comprehensive educational reference for beginner engineers using industry-standard methodologies and tools. The study was developed as a final assignment for a physical design course and was supported by the IC Inovador Training Project - an initiative involving the Ministry of Science, Technology and Innovation, Softex, the Federal University of Campina Grande (UFCG), and the Federal University of Santa Maria (UFSM). It now also supports undergraduate work at the Federal University of Rio Grande do Norte (UFRN). The methodology employs Cadence EDA (Electronic Design Automation) tools - Xcelium, Genus, Innovus, Virtuoso, and Modus - for simulation, synthesis, implementation, and testing, respectively. These tools were chosen exclusively because they were provided by the residency project, not as a result of a comparative analysis with other available solutions.