Análise de eficiência energética e caracterização da plataforma GAP8

Abstract

Dynamic reduction of voltage margins is an energy-efficient technique that is being used on recent platforms. This course conclusion work proposes to explore the possibility of performing calculations and working with high frequency processing efficiently. The platform used for testing was the GAPuino GAP8 board based on the PULP Project (Parallel Ultra Low Power) by ETH Zurich. It was designed and implemented to have low energy consumption, in addition to its construction being close to the final objective of the CEVERO project (Multiprocessor Chip for Very Energy efficient aeRospace missiOns), which aims to produce a fault-tolerant System On Chip (SOC) for satellite embedded applications. The analyzes carried out in this research observe that it is possible to work at high frequencies, above the guardband of the board, thus verifying time and energy savings. The main methodology used to investigate this behavior was the change in runtime of the voltage and, accompanying this, the frequency, to levels considered unsafe by the manufacturer. The findings made here are based on data views that were generated throughout the study, along with performance measurement directly on the platform during runs.