Análise da Implementação de Redes Neurais em Hardware Utilizando hls4ml no Contexto do LHC L1 Trigger

Abstract

With the anticipated increase in data rate and complexity at the LHC after the upgrade to HL-LHC, advanced machine learning techniques are being explored to ensure adequate latency and performance, particularly in the selection of relevant events (triggers) for the CMS and ATLAS experiments. The implementation of neural networks in field-programmable gate arrays enables real-time analysis with latencies on the order of nanoseconds, surpassing the latency limitations of GPUs. However, this approach presents significant challenges in terms of resource consumption and physical space, as underground detector systems have limited FPGA capacity and must execute thousands of tasks simultaneously. To meet resource constraints, techniques such as model quantization and compression are applied to reduce neural network sizes without compromising latency. Additionally, due to the long development time required for HDL implementation, high-level synthesis (HLS) tools have been adopted to automate the hardware description process. In this context, the hls4ml library uses HLS to convert neural network models developed in Python to HDL, streamlining and accelerating development. This work presents an evaluation of the hls4ml library’s features, examining how it can be used to optimize neural networks in hardware to meet the LHC L1 trigger requirements, reducing latency and resource usage without significant performance loss.