Projeto e implementação de um acelerador de arquitetura reconfigurável

Abstract

In the field of Computer Science performance is a hard-sought feature for both software and hardware. For so, there are studies of data types, heuristics, metaheuristics, language updates, compilers and softwares that seek to improve the performance at the logical level. In addition to those, also exists updates, research and development of increasingly efficient hardware. Decreasing the size of transistors, greater number of cores and multithread support are examples of advances achieved in this area. Also, in this view, the Reconfigurable Array was created, an accelerator that uses the reconfigurable architecture paradigm. Such array consists in a series of parallel aritmetic and logic units (ALUs), multipliers and memory access units, in order to make several sorts of applications more efficient. In this context, this work consits on the research, project and implementation of a Reconfigurable Architecture Array, to accelerate the execution of general purpose applications, using the hardware description language VHDL to simulate the created system. Differentt accelerator architectures will be investigated, then an architectural design will be proposed, implemented, validated and tested.